1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for multivariate fault detection and classification.
2. Description of the Related Art
To fabricate a semiconductor device, a wafer is typically processed through numerous processing tools in a predetermined sequence. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal anneal tools, ion implantation tools, and the like. Each processing tool modifies the wafer according to a particular operating recipe and/or operating parameters. For example, a photolithography stepper may be used to form a patterned layer of photoresist having a predetermined thickness above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. Metrology tools may be used to collect inline data from the wafer before, during, or after processing by one or more of the tools. For example, the metrology tool may determine a critical dimension of one or more of the gate electrode structures formed above the surface of the wafer.
Despite the quantity of inline data that is collected as wafers are processed down the manufacturing line, the inline data does not typically provide a complete indication of how completed devices will perform when they are tested at the end of the line. Even when individual processes are performing within their specifications, poor device performance can result from cumulative effects from multiple tools and operations. Additionally, some process disturbances may not be detected using the inline data because of inadequacies in the fault detection and classification (FDC) system or due to the existence of disturbances that cannot be measured by existing technology. Accordingly, the completed wafers are typically tested using a post-processing testing unit, such as a wafer electrical test device.
A wafer electrical test device may be used to measure numerous electrical parameters associated with the semiconductor devices formed on the wafer. For example, the wafer electrical test device may measure voltages and/or currents associated with gate electrode structures, or electrical circuits including a plurality of interconnected structures, formed on the surface of the wafer. If one or more of the measured electrical parameters falls outside of a predetermined range or tolerance, a notification may be sent to an engineer monitoring the manufacturing line. For example, a monitoring system may send an e-mail to the engineer monitoring the manufacturing line indicating which of the measured electrical parameters has fallen outside of the predetermined range or tolerance, as well as which wafer included the structure. The engineer may then access data associated with the out-of-range electrical parameter and attempt to diagnose and/or fix faults that may have produced the out-of-range electrical parameter.
The data associated with the measured electrical parameters are typically presented and analyzed as univariate data. For example, a voltage associated with a gate electrode structure formed on each of a plurality of wafers may be presented in a plot of the voltage as a function of wafer number. The plot may also include one or more boundaries or lines indicating an allowable or acceptable range or limit for the voltage. The engineer may then review the voltage plot to determine which wafers include gate electrode structures that produced voltage parameters outside the allowable and/or acceptable range. The engineer may initiate some kind of corrective action, such as scrapping the wafers that include the gate electrode structures that produced the undesirable voltage parameters or altering an operating recipe used to produce the faulty structure.
A typical wafer electrical test device used to monitor performance of semiconductor devices formed on a wafer may collect information associated with about 200 different parameters. In some cases, as many as about 700 parameters may be measured. Accordingly, it may be difficult or impossible for engineers to monitor all of the parameters measured by a wafer electrical test device. For example, engineers may monitor a subset of approximately 40 of the 200 different parameters using a univariate statistical process control (SPC) method. The subset of the parameters may be considered to be the most important parameters or the parameters most likely to indicate a fault and/or warning. Moreover, the indications of allowable and/or acceptable ranges for the parameters used in the SPC method are typically determined by the engineers, which may be a very time-consuming task. Reviewing univariate data may also cause engineers to miss faults and/or warnings associated with correlations between different parameters.
End-of-line monitoring tools typically lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender non-optimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
The present invention is directed to addressing the effects of one or more of the problems set forth above.